Digital logic design

Finite State Machine Generator

Design a binary-input finite state machine online. Edit states and transitions, visualize the diagram, simulate input sequences, and export the design as CSV, SVG, or Verilog.

1. Machine settings

Machine type

Initial state

Verilog module name

Input signal name

Output signal name

2. Edit states and transitions

Each state has a destination for input 0 and input 1. Moore output belongs to the state; Mealy output belongs to the transition.

3. State diagram

The orange arrow marks the initial state. Transition labels show input values, or input/output pairs for Mealy machines.

4. Transition table

5. Simulate an input sequence

Enter a sequence containing only 0 and 1, for example 101101. The simulation begins in the selected initial state.

6. Verilog HDL generator

Generate a starting-point HDL implementation from the current machine. Review and test the code in your HDL simulator before using it in hardware.

What is a finite state machine?

A finite state machine (FSM) represents a system using a finite set of states and transitions. The current state and input determine the next state. FSMs are common in digital electronics, control systems, communication protocols, and embedded software.

Moore and Mealy machines

Moore machine: the output is determined by the current state.
Mealy machine: the output is determined by the current state and input.

How to use this tool

Choose the machine type and initial state.
Add or rename states and configure transitions for input 0 and input 1.
Check the generated diagram and transition table.
Run a binary input sequence through the simulator.
Export the table or diagram, or generate Verilog code.

Frequently asked questions

What does the generator produce?

It produces a state diagram, transition table, binary input simulation, CSV table, SVG diagram, and Verilog starting point.

What is a sequence detector?

A sequence detector is an FSM that recognizes a specified pattern of input bits, such as 101, while processing a stream of binary data.

Can I use the generated Verilog directly in an FPGA?

Review the code and verify its reset, clock, and output behavior. Compile and simulate it for your target design before using it on hardware.

Does this tool need a database?

No. Editing, drawing, simulation, and downloads run in your browser and do not require a database or form submission.